library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity latch_IFID is
    port (
        iPC    : in  std_ulogic_vector(15 downto 0);
        oPC    : out std_ulogic_vector(15 downto 0);
        iINS   : in  std_ulogic_vector(15 downto 0);  --instruction
        oINS   : out std_ulogic_vector(15 downto 0);  --instruction
        clk    : in  std_ulogic;
		rst	   : in  std_ulogic;
        enable : in  std_ulogic
        );
end latch_IFID;

architecture Behavioral of latch_IFID is
    component latch16
        port (
            i      : in  std_ulogic_vector(15 downto 0);
            o      : out std_ulogic_vector(15 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
begin
    U_PC  : latch16 port map(iPC, oPC, clk, rst, enable);
    U_INS : latch16 port map(iINS, oINS, clk, rst, enable);
end Behavioral;

